1. Field of the Invention
The present invention relates to butting contact structures, and, more particularly, to reducing the area of butting contact structures such as those employed in static random access memory (RAM) cells.
2. Description of the Related Art
Butting contact structures form an electrical connection between doped regions in a silicon layer and one or more polysilicon layers. They are especially useful in four-transistor static RAM cells where an electrical connection is required between layers of polysilicon and the doped silicon region.
In the conventional four-transistor static RAM cell, a butting contact is made by patterning a gate polysilicon layer (gate poly) with an underlying gate oxide lying over a doped silicon region and covering the entire region, including the gate poly, with an oxide, such as silicon dioxide. A contact hole is then etched in the oxide exposing portions of both the gate poly and the doped silicon region. This particular contact hole, usually referred to as a quasi-buried contact, is distinct from the contact hole used to connect a first metal layer to underlying layers.
A polysilicon layer, called the load poly, is then deposited on top of the exposed portions of both the gate poly and the doped silicon region. This poly layer is then patterned and selectively doped in the vicinity of the contact hole to make electrical contact to and between the gate poly and the doped silicon region.
This contact structure requires a large layout area because the load poly must cover the contact hole entirely even under the worst-case conditions of misalignment and other process variations. If the contact hole is not completely covered by the load poly, then either a portion of the doped silicon region or the gate poly may be etched away when the load poly is defined and etched, which can lead to improper operation of the memory cell.